Automatic detection of MOS synchronizers for timing verification

Static timing verifiers need to know at which points data are synchronized with clocks in a circuit. Typically, this happens at latches and in clock qualification gates. However, in a general, full-custom VLSI methodology, the 'latch-equivalents' are far more varied and difficult to detect reliably. The authors define these synchronization points, and present provably robust algorithms to locate them in a very general class of MOS networks, including arbitrary pass gates. The algorithms have been applied to a variety of full-custom CPUs of up to 500 K devices, and have been found to work extremely reliably and quite fast.

Full Article in IEEE International Conference on Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991