A method and
apparatus for preventing system wide data dependent stalls is provided. Requests
that reach the top of a probe queue and which target data that is not contained
in an attached cache memory, are stalled until the data is filled into the
appropriate location in cache memory. Only the associated central processor
unit's probe queue is stalled and not the entire system. Accordingly, the
present invention allows a system to chain together two or more concurrent
operations for the same data block without adversely affecting system
performance (Full Patent Here).