A data
caching system and method includes a data store for caching data from a main
memory, a primary tag array for holding tags associated with data cached in the
data store, and a duplicate tag array which holds copies of the tags held in
the primary tag array. The duplicate tag array is accessible by functions, such
as external memory cache probes, such that the primary tag remains available to
the processor core. An address translator maps virtual page addresses to
physical page address. In order to allow a data caching system which is larger
than a page size, a portion of the virtual page address is used to index the
tag arrays and data store. However, because of the virtual to physical mapping,
the data may reside in any of a number of physical locations. During an
internally-generated memory access, the virtual address is used to look up the cache.
If there is a miss, other combinations of values are substituted for the
virtual bits of the tag array index. For external probes which provide physical
addresses to the duplicate tag array, combinations of values are appended to
the index portion of the physical address. Tag array lookups can be performed
either sequentially, or in parallel (Full Patent Here).