Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation

Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored. A two-state version of simulation code for the circuit design, the two states corresponding to 0, and 1 is generated. For each phase of a module for which no event-based evaluation need be performed, the stored response with respect to corresponding module of the three-state version is determined and stored (Full Patent Here).